About Me
Hi, I am a Ph.D. candidate at ICT, CAS, advised by Prof. Gaogang Xie and Prof. Quan Yu. Throughout this timeframe, under the mentorship of Layong Luo, I actively engaged in designing and implementing a variety of real-world applications(Tiara, SRNIC, Faery). Before that, I received my B.Eng in Computer Science in Huazhong University of Science and Technology (HUST) in 2019.
My research interests include high-performance datacenter networking (eg., RDMA) and software-hardware codesign for application acceleration.
Interests
- RDMA-related Technique.
- Software-hardware Co-design.
- FPGA Acceleration.
Education
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PhD in Computer Architecture, 2019 -
Institute of Computing Technology, Chinese Academy of Sciences
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BSc in Software Engineering, 2015 - 2019
Huazhong University of Science and Technology
Selected Publications
Fast, Scalable, and Accurate Rate Limiter for RDMA NICs
Zilong Wang, Xinchen Wan, Luyang Li, Yijun Sun, Peng Xie, Xin Wei, Qingsong Ning, Junxue Zhang, Kai Chen In Proc. SIGCOMM'24
Tiara: A Scalable and Efficient Hardware Acceleration Architecture for Stateful Layer-4 Load Balancing
Chaoliang Zeng, Layong Luo,Teng Zhang, Zilong Wang, Luyang Li, Wenchen Han, Nan Chen, Lebing Wan, Lichao Liu, Zhipeng Ding, Tao Feng, Feng Ning, Kai Chen, Chuanxiong Guo In Proc. NSDI'22
Experience
Intern
Bytedance
Projects include:
- Designing and developing scalable and efficient security gateways.
- Designing and building a basic platform for heterogeneous FPGAs in the cloud.
- Cutting-Edge Research.
Skills
HDL(Sytem Verilog)
Emulation(Cocotb)
Python